Vieweg+teubner Verlag
Enhancing Embedded Systems Simulation: A Chip-Hardware-In-The-Loop Simulation Framework
$128.71
VDM Verlag Dr. Mueller E.K.
Hardware-in-the-Loop Simulation
Product Code:
9783836462167
ISBN13:
9783836462167
Condition:
New
$63.72
$63.18
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Hardware-in-the-Loop Simulation
$63.72
$63.18
Sale 1%
Safety-critical real-time systems must guarantee correct operation in all operational conditions - even if these conditions are very unlikely to occur (rare events). Hardware-in-the-Loop (HiL) simulation is a common validation technique of real-time systems. In an HiL simulation the environment of a System-Under-Test (SUT) is simulated by an assigned HiL simulator. Thereby, the SUT interacts with the HiL simulator in real-time which necessitates a model of time and interfaces of the HiL simulator that are identical to the model of time and the interfaces of the SUT. In this book an HiL simulation framework is proposed that allows predictable interaction of a distributed HiL simulator and an SUT. This HiL simulation framework comprises configurable simulation components which are interconnected via a time-triggered interaction mechanism. Information flow between the HiL simulator and the SUT is strictly controlled by the progression of synchronized global time and bound to a priori known latency and jitter. This book addresses researchers and engineers in safety-critical domains such as the avionics or automotive industries.
| Author: Martin Schlager |
| Publisher: VDM Verlag Dr. Mueller E.K. |
| Publication Date: Apr 21, 2008 |
| Number of Pages: 152 pages |
| Binding: Paperback or Softback |
| ISBN-10: 3836462168 |
| ISBN-13: 9783836462167 |
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