This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
| Author: Zheng Wang, Anupam Chattopadhyay |
| Publisher: Springer |
| Publication Date: Jul 05, 2017 |
| Number of Pages: 197 pages |
| Language: English |
| Binding: Hardcover |
| ISBN-10: 9811010722 |
| ISBN-13: 9789811010729 |
